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SIP封装新闻-三星计划积极推出下一代晶体管

三星计划积极推出下一代晶体管| EE Times

加利福尼亚州圣克拉拉 - 三星的代工部门周二提供路线图更新技术,包括其即将推出的3-nm全能门(GAA)技术的第一个工艺设计套件。公司高管还提供了有关高级3D的一些细节包装技术并引入了新的基于云的设计环境。

Samsung plans to begin risk production of one of two 3-nm GAA processes that it plans to offer by the second half of next year, with mass production expected in 2021. The company plans to begin risk production of the next 3-nm GAA process in 2021, with mass production expected in 2022.三星计划在明年下半年开始风险生产其计划提供的两种3-nm GAA工艺之一,预计将于2021年开始量产。该公司计划开始风险生产下一个3-nm GAA工艺在2021年,预计在2022年大规模生产。

Last month, Samsung began volume production on its 7-nm FinFET process, the first to make use of next-generation extreme ultraviolet (EUV) lithography. While the company plans to roll out derivative 6-, 5- and 4-nm processes with FinFETs over the next two to three years, Samsung considers 3 nm to be its next major process technology node and the first that will use GAA 3D multibridge-channel FETs, which feature gate material surrounding the channel region on all sides.上个月,三星批量生产其7纳米FinFET工艺,率先采用下一代极紫外(EUV)光刻技术。该公司计划推出衍生的6纳米,5纳米和4纳米工艺。在接下来的两到三年内,三星认为3纳米是主要工艺技术节点的旁边,而第一个使用GAA 3D多桥通道FET,其四周都是围绕通道区域的材料。

Voltage scaling of FinFET technology runs out of steam at 0.75 V at the 10-nm node. Samsung is implementing its GAA technology — which utilizes nanosheets as opposed to nanowires, enabling greater current per stack — to reduce the operating voltage to 0.7 V, said Yongjoo Jeon, a principal engineer with Samsung's foundry marketing team. Conventional GAA with nanowires requires a larger number of stacks due to its small effective channel width.三星正在实施其GAA技术 - 利用纳米片,因为它具有每堆高电流 - 将工作电压降低至0.7 V,因为FinFET技术的电压缩放在10-nm节点处耗尽0.75 V的蒸汽。由于纳米线的有效通道宽度较小,传统的纳米线GAA需要大量的堆叠。三星的首席工程师Yongjoo Jeon。

Samsung said that it released its first process design kit (PDK) — version 0.1 — for its initial 3-nm GAA process last month.三星表示上个月推出了其首款3-nm GAA工艺流程设计套件(PDK) - 版本0.1。

“As far as I know, we are the only company that has a plan for putting gate-all-around in production,” Jeon said. “据我所知,我们是唯一一家有计划全面投入生产的公司,”Jeon说。

ES Jung, president of Samsung's Foundry Business, speaks at the company's Foundry Technology Forum Tuesday in Santa Clara.三星铸造业务总裁ES Jung周二在Santa Clara的公司铸造技术论坛上发表讲话。

TSMC is planning to introduce its version of GAA technology at the 5-nm node but has not announced a target date for putting the technology into production.台积电计划在5纳米节点上推出其GAA技术版本,但尚未宣布投入该技术的目标日期。

Samsung has about a one-year lead in GAA over TSMC, thanks to its heavy investment in R&D on advanced materials, including graphene, said Handel Jones, CEO of International Business Strategies. “Samsung is in a leadership position in 3-nm GAA, and the key advantage is due to internal access to the materials for nanosheet structures,” Jones said.国际商业策略公司首席执行官汉德尔·琼斯表示,由于对包括石墨烯在内的先进材料的研发投入大量投资,三星在台积电的GAA上已有一年多的领先优势,“三星在3-nm GAA中处于领先地位,而关键的优势在于内部可以获得纳米片结构的材料,“琼斯说。

Samsung said that it recently taped out a test vehicle for the first 3-nm GAA process, known as 3-nm GAE, which offers a 45% reduction in chip area, 50% lower power consumption, or 35% higher performance compared to its 7-nm process. Executives expect the process to be popular for compute-intensive applications, including mobile, network, automotive, AI, and IoT.三星表示,最近推出了第一款3-nm GAA工艺的测试车,称为3-nm GAE,芯片面积减少45%,功耗降低50%,性能提升35%。 7纳米工艺。管理人员希望该工艺在计算密集型应用中广受欢迎,包括移动,网络,汽车人工智能物联网

“GAA will support analog functionality as well as digital, which gives it an advantage over FinFETs,” Jones said. “GAA will consequently have a long lifetime and with multiple versions in device structures even though lithography does not shrink.” “GAA将支持模拟功能以及数字功能,这使其具有优于FinFET的优势,”Jones Said说道。“GAA将具有较长的使用寿命,并且在器件结构中具有多个版本,即使光刻技术不会缩小。”

· 2019-05-17 09:28  本新闻来源自:eetimes,版权归原创方所有

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