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芯片封装路线图减速,发散

ANTWERP-下一代晶体管可能采用英特尔三星台积电的风格。这只是半导体路线图如何展开的一个标志,因为它已经发布了前面几个节点的墙。

At an annual event here , Imec researchers laid out what one observer called “a Cambrian explosion” of options to squeeze advances out of silicon. They span new kinds of transistors, materials, architectures and packages. Imec研究人员在这里展示了一个事件 ,他们将一个观察者所谓的“寒武纪爆炸”称为“挤压硅片的先进技术”。它们涵盖了各种晶体管,材料,架构和封装

“Generic devices may no longer be possible…the one-dimensional roadmap may not be sufficient anymore. The future is not clear, but we need more options,” Luc van den Hove, chief executive of the research institute, said in a keynote.未来尚不清楚,但我们需要更多选择,“研究机构首席执行官Luc van den Hove在主题演讲中表示。”“通用设备可能不再可能......一维路线图可能还不够。

Engineers will need all the knobs and levers they can get given a sobering roadmap Imec showed. It forecasts feature sizes will plod forward with shrinks at a pace measured in single-digit nanometers for the next few nodes. Beyond 40nm gate lengths and 16nm metal pitches at a 2-nm node, they may not shrink at all.它将包含在接下来几个节点的下一代节点中。工程师将需要所有的旋钮和杠杆,因为Imec显示了一个清醒的路线图。在2纳米节点,它们可能根本不会收缩。

Researchers showed a frank and aggressive road map with an N7 similar to current foundry N5 nodes.Click to enlarge. (All images: Imec)(所有图片:Imec)研究人员展示了一个坦率而积极的路线图,其中N7与目前的代工厂N5节点类似。点击放大。

The result is chip performance may no longer scale for the highest-end parts. Shy of the top-end in active power, advances still are possible, especially for those willing to switch from FinFETs to more compact nanosheet transistors.对于有源功率方面的高端产品,仍然有可能取得进展,特别是那些愿意从FinFET转向更紧凑的纳米片晶体管的人。

Chip makers focused on area and power shrinks for mobile systems may cling to FinFETs as long as possible. Those most hungry for performance gains will shift early to nanosheets that Imec expects will eke out an extra 8% in frequency, sacrificing reductions in area.专注于移动系统面积和功率缩小的芯片制造商可能会尽可能长时间地依赖FinFET。那些最渴望获得性能提升的人将会提前转向纳米片,预计频率将增加8%,牺牲性降低。

Nanosheets will have an emerging mid-life kicker in what Imec calls the forksheet, a design still being defined that pushes n- and p- devices closer together. The ultimate in compact transistors is a complementary or vertical FET that could get down to four or even three tracks by stacking n and p elements.纳米片将在Imec所谓的forksheet中有一个新兴的中年生产者,这种设计仍然被定义为将n和p器件推得更紧密。紧凑型晶体管的最终结构是互补或垂直FET,覆盖其他通过堆叠n和p元素甚至三个轨道。

Along the way, engineers may try to push spacers to k values as low as 3.3 or even make a mad leap to geranium structures. “It's a lot of each going their own way,” said Julien Ryckaert, director of Imec's logic scaling program. “每个人都有自己的方式,”Imec的逻辑推理主管Julien Ryckaert说道。

Designers working at standard cells and higher levels can ignore the transistor variations but will face extra cross-checks if they want to change foundries. Fabless companies with their own memory macros and cell libraries will need to be “profoundly aware of what's happening on the technology side,” said Diederik Verkest, an Imec program director.在标准单元和更高级别工作的设计人员可以忽略晶体管的变化,但如果他们想要改变代工厂则会面临额外的交叉检查。拥有自己的存储器宏和单元库的法布里公司将需要“深刻意识到” “Imec项目总监Diederik Verkest说道。

· 2019-05-17 09:13  本新闻来源自:EE Times,版权归原创方所有

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