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用于高性能计算的高级异构封装解决方案

异构集成电路(IC)封装已经完全进入高性能计算领域。 目标应用广泛,涉及人工智能(AI),深度学习,数据中心网络,超级计算机和自动驾驶等领域。 事实上,新一代深度学习AI,领先的数据中心服务器中央处理器(CPU)以及最新刀片服务器的性能领先CPU,这些卓越的IC封装结构已经成为可能。

这些尖端技术正在引领令人难以置信的进步。 此外,它们都具有共同的特征:高速,高性能IC。

投资机构高盛集团(Goldman Sachs Group)预测全球人工智能硬件微芯片(包括CPU,图形处理器(GPU),专用集成电路(ASIC),现场可编程门阵列(FPGA)等)将以每年的复合速率增长未来几年将超过40%(图1)。

图1.全球AI计算硬件总可用市场(TAM)(资料来源:Goldman Sachs 2018)

在深度学习中,算法和大数据可访问性的不断进步与基于异构IC封装的高性能计算引擎相结合,正在推动这一技术浪潮的巨大飞跃。 该封装结构使之前可能实现了两倍的飞跃,特别是:由于三星和海力士推出的高带宽内存 (HBM),以及提供更多封装外信令容量的能力,提高了内存带宽。

异构包装方法

FCBGA MCM

使用倒装芯片BGA (FCBGA)封装的异构数字集成已经发生多年,并且各种方法几乎无穷无尽。 多芯片模块(MCM)的管芯内路由功能很好,只要能够实现这一目标的层数,它将继续成为许多设备的可行方法。

TSV

硅通孔(TSV)开发花费了数年时间才完善硅插入器,但真正迎来了现代异构浪涌。 其影响是深远的,因为可用的最高带宽DRAM(HBM)专门设计用于硅中介层应用。 这种新的性能水平仅适用于2.5D TSV封装:首先是超高性能图形,然后是深度学习加速器,现在是数据中心网络交换机和服务器CPU。 硅中介层的主要要求是HBM器件使用超宽1024位并行总线,需要2μm宽或更小的信号路由走线。 这是FCBGA基板的布线密度的8-10倍。

Amkor的TSV显示工艺和芯片上芯片(CoW)封装已经在大批量生产(HVM)中使用了三年。 装配过程是位于韩国Song-Do,仁川国际机场附近的新型超洁净K5工厂的高产旗舰。 图2显示了这种封装技术的典型实现的关键要素。

图2.高级2.5D封装技术的三个关键要素。

HBM:刚刚开始

在2.5D TSV封装结构中与HBM结合使用的处理器排在第一位,但这仅仅是开始。 今天,7nm和即将推出的5nm设计的成本将使得重点放在片上系统(SoC),ASIC或处理器的内容上。超越单个SoC方法的领先优势是处理器和多个分立I / O芯片甚至多个处理器芯片的封装内组合,以增加内核数量和离散I / O芯片。 目前的几个例子已经过原型设计和宣布。

新级别的器件性能和异构IC封装结构之间的关键交叉点之一是管芯内信号路由功能。 2.5D内插器提供铜后端双镶嵌技术,具有出色的细线能力和短时间运行的合理电信号性能。 今天,2.5D TSV是HBM集成到您的产品设计中的可靠途径。

另一种即将到来的技术使用所谓的“最后一次死亡”,高密度扇出(HDFO)方法。

HDFO包装

正在开发HDFO封装作为异构集成的另一个关键支柱,以降低高性能异构应用的成本。 这种细线再分布层(RDL)方法能够实现2μm线/间距和4层计数,以提供管芯间布线。 在这种情况下,铜/有机电介质RDL层制造在玻璃或硅载体上,然后晶片装有功能性管芯并以非常类似于2.5D设计的方式模制(图3)。

图3:高密度扇出解决方案。

对于2.5D封装设计方案,设计流程和设计方法与传统封装设计有很大不同。 例如,具有4,000个凸块的HBM2 DRAM和主芯片可能具有数万个凸块和多个芯片,通过内插器连接。 为此,需要推进设计,优化模拟和规则检查。 为应对这些挑战,Amkor已经开发了外包半导体装配和测试(OSAT),业界领先的工艺装配设计套件 (PADK),以及与Cadence和Mentor Graphics实现电子设计自动化(EDA)连接的设计流程。

该套件在设计阶段引入并实现异步调试设计环境,以便在原理图和布局图之间进行比较,并执行所有设计规则检查(DRC)。 该过程实现了严格的设计验证和签核。 此外,通过提取设计,插入器和基板模型,实现协同设计和协同仿真,性能设计(DFP),成本设计(DFC)和制造设计(DFM),也实现了。 图4显示了模拟眼图的一个示例,其中HBM数据总线以2 GHz频率工作。

图4.显示共同封装的ASIC和HBM2性能的眼图。

摘要

异构软件包克服了单片集成的现有限制,显着提高了当今电子产品的功能和性能。 随着硅集成面临更多甚至更加困难的挑战,向异构封装迈出的下一步将发挥更大的作用,将最终产品推向更高水平。 目前,包装解决方案可用于使下一代产品成为现实。


编者注:本文由Ron Huemoeller,Mike Kelly,Curtis Zwenger,Dave Hiner和George Scott,Amkor Technology,Inc。首次出现在3D InCites:The First Decade中。

原文:

Heterogeneous integrated circuit (IC) packaging has made a full entrance into the high-performance computing arena. The target applications are broad, running the gamut from artificial intelligence (AI), deep learning, data center networking, supercomputers, and autonomous driving. In fact, a new generation of deep learning AI, leading central processing units (CPUs) for data center servers as well as new performance-leading CPUs for the latest blade servers have literally been made possible by these remarkable IC package constructions.

These cutting-edge technologies are leading the way for incredible advancements.Moreover, they all have a common characteristic: high-speed, high-performance ICs.

Investment agency Goldman Sachs Group has predicted that global AI hardware microchips including CPUs, graphics processing units (GPUs), application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs) and others, will grow at an annual compound rate of more than 40% in the coming years (Figure 1).

Figure 1. Worldwide AI computing hardware total available market (TAM) (Source: Goldman Sachs 2018)

In deep learning, continuous advancements in algorithms and big data accessibility combined with high-performance compute engines based on heterogeneous IC packaging are driving the giant leap forward for this technology wave. The package construction has permitted a two-fold leapfrog in what was possible previously, specifically: a memory bandwidth improvement thanks to high bandwidth memory (HBM) introduced by Samsung and Hynix, and the ability to provide more off-package signaling capacity.

Heterogeneous Packaging Approaches

FCBGA MCM

Heterogeneous digital integration using flip chip BGA (FCBGA) packages has been occurring for years and the variety of approaches has been nearly endless. The intra-die routing capability for multichip modules (MCMs) is good, and as long as the layer count to achieve this can be accommodated, it will continue to be a viable approach for many devices.

TSV

Through-silicon via (TSV) development took several years to perfect in silicon interposers but really ushered in the modern heterogeneous surge. The implications were profound, as the highest bandwidth DRAM (HBM) available were designed exclusively for silicon interposer applications. This new performance level was only available in 2.5D TSV packages: first in ultra-performance graphics, then deep-learning accelerators and now in data center networking switches and server CPUs. The main requirement for silicon interposers is that the HBM device uses an ultra-wide 1024-bit parallel bus requiring signal routing traces of 2µm width or smaller. This is 8-10 times the routing density of an FCBGA substrate.

Amkor's TSV reveal process and chip-on-wafer (CoW) packages have been in high-volume manufacturing (HVM) for three years. The assembly processes are high-yielding flagships of the new ultra-clean K5 facility in Song-Do, South Korea, near the Incheon International Airport. Figure 2 shows the key elements of a typical implementation of this packaging technology.

Figure 2. Three key elements of advanced 2.5D packaging technology.

HBM: Just the Beginning

Processors used in conjunction with HBM in 2.5D TSV packaging constructions came first, but this is viewed as just the beginning. Today, the expense of 7nm and upcoming 5nm design will sharpen the focus for the content placed into the system-on-chip (SoC), ASIC or the processor. Leading advancements beyond single SoC approaches are in-package combinations of the processor and multiple discrete I/O die and even multiple processor chips in an effort to increase the core count and discrete I/O die. Several current examples of these have been prototyped and announced.

One of the key intersections between new levels of device performance and heterogeneous IC package structures is the intra-die signal routing capability. The 2.5D interposer offers a copper back-end dual-damascene technology with excellent fine-line capability and reasonable electrical signaling performance for short runs. Today, 2.5D TSV is the proven path for HBM integration into your product designs.

Another up and coming technology uses the so-called “dies-last,” high-density fan-out (HDFO) approach.

HDFO Packaging

HDFO packaging is being developed as another crucial pillar for heterogeneous integrations to lower the cost of high-performance heterogeneous applications. This fine-line redistribution layer (RDL) approach is capable of 2µm line/space and 4-layer counts to provide the inter-die routing. In this case, the copper/organic dielectric RDL layers are fabricated on a glass or silicon carrier and then the wafer is populated with functional die and molded in a manner very similar to 2.5D designs (Figure 3).

Figure 3: A high-density fan-out solution.

For the 2.5D package design plan, the design flow and design methodology are very different from traditional package designs. For example, an HBM2 DRAM having 4,000 bumps, and the main chip maybe having tens of thousands of bumps and multiple chips, are connected through an interposer. To do this, the design, simulation for optimization, and rule-checking need to advance. Addressing these challenges, Amkor has already developed outsourced semiconductor assembly and test (OSAT), industry-leading process assembly design kits (PADKs), and a design flow to achieve electronic design automation (EDA) connectivity with Cadence and Mentor Graphics.

The kits are introduced during the design stage and achieve asynchronous debugging design environment to carry out comparisons between schematic and layout diagrams and to perform all design rule checks (DRCs). This process achieves rigorous design verification and sign-off. In addition, by extracting the design, interposer and substrate models, and implementing co-design and co-simulation, design-for-performance (DFP), design-for-cost (DFC) and design-for-manufacturing (DFM), are also achieved. Figure 4 shows one example of a simulated eye-diagram, with the HBM data bus operating at 2 GHz frequency.

Figure 4. Eye diagram showing the performance of co-packaged ASIC and HBM2.

Summary

Heterogeneous packages have overcome the existing limitations of monolithic integration and significantly increased the capabilities and performance of today's electronic products.As silicon integration faces additional and even more difficult challenges, the next step towards heterogeneous packaging will fulfill an even greater role to take end products to ever higher levels. The packaging solutions are available today to make the next generation products a reality.

· 2019-04-28 11:40  本新闻来源自:3D InCites,版权归原创方所有

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